1. Technical Field
The present invention relates to a semiconductor device, a process for manufacturing a semiconductor device and a power amplifier element.
2. Related Art
When an element is assembled via a wire bonding process for power amplifier elements (discrete, integrated circuit (IC)), a gain of the power amplifier deteriorates due to an inductance of the wire. Such gain deterioration is considerably exhibited in an emitter terminal or in a ground (Gnd) terminal of IC. Such deterioration of the gain is caused because voltage between a base and an emitter (VBE) in an output a transistor is reduced due to an inductance of a wire coupled in series to the emitter. For example, a bonding wire having a length of 0.3 mm has an inductance of about 0.2 nH. When an alternating current of 100 mA amplitude is applied at 2.4 GHz through such bonding wire, a decrease of the gain of 4 dB is estimated due to a deterioration of VBE. A structure for utilizing a semiconductor substrate as a GND (earth) without utilizing a bonding wire for an emitter, in order to reduce the deterioration of the gain, is disclosed. The use of such structure allows an electric current path to a semiconductor substrate having lower inductance and lower resistance.
A typical conventional technology will be described. A plan view of a semiconductor device according to a conventional technology is shown in FIG. 6A. FIG. 6B is a cross-sectional view along line B-B′ of FIG. 6A. A constitution of a wafer (substrate) includes a P-type substrate 101 and a P-type epitaxial layer 103 formed thereon, and further an N-type epitaxial layer 105 formed thereon. A substrate contact 107 may be formed as follows. An etching process is conducted from a wafer surface to the P-type substrate 101, and then the etched feature is filled with a high-concentration doped polysilicon 109. Further, a terminal is provided on the high-concentration doped polysilicon 109 in the substrate contact 107. Japanese Patent Laid-Open No. H11-214,398 (1999) describes a structure similar to the above-described structure, though a manner for creating a contact 111 is not clearly presented. An electrically conducting path routes from the contact 111 in the side of the upper surface of the wafer through the high-concentration doped polysilicon 109 to be coupled to the P-type substrate 101.
Further, Japanese Patent Laid-Open No. S59-232,439 (1984) described a structure of a semiconductor device as shown in FIG. 7D. FIGS. 7A to 7D show a manufacturing process for such semiconductor device. In the formation of a metal oxide semiconductor (MOS) IC, an N-type silicon epitaxial layer 202 and an oxide film 203 are consecutively formed on a P-type silicon substrate 201. Further, a resist film 204 having an opening width 205 corresponding to the element isolating region width is formed on the oxide film 203. A U-trench 206 extending through the oxide film 203 to the P-type silicon substrate 201 is formed via an etching process (FIG. 7A). Then, an ion implantation of boron (B) is conducted to selectively form a high-concentration Boron-implanted region 207 in an inner surface, particularly in the bottom surface of the U-shaped trench 206 (FIG. 7B). After the resist film 204 is removed, an undoped silicon is selectively grown on an inner surface of the U-shaped trench 206 having a silicon section exposed thereon, which has been created in the U-shaped trench 206 via an ordinary selective epitaxial growth technique conducted at a temperature of around 1,000 degrees C. Simultaneously, an auto-doping of Boron is caused in the silicon epitaxial layer from a high-concentration Boron-implanted region 207 to form P+ type silicon epitaxial layer 208 in the U-shaped trench 206 (FIG. 7C). Lastly, an oxide film 209 is formed on the surface of the P+ type silicon epitaxial layer 208 (FIG. 7D). It is disclosed that the element isolation region of the semiconductor device is formed by the above-mentioned process.
Further, Japanese Patent Laid-Open No. H5-109,884 (1993) describes a configuration of a semiconductor device, which is manufactured by the following manufacturing process illustrated in FIGS. 8A to 8C and FIGS. 9A to 9C. A semiconductor layer 303 for a silicon on insulator (SOI) substrate (referred to as the semiconductor layer 303 for a SOI substrate for a combination of an N+ type silicon layer and an N-type epitaxial silicon layer) is disposed on the N+ type silicon support substrate 301 through an oxide film 302 for SOI. A U-shaped trench 306 for contacting with the substrate, which extends through the semiconductor layer 303 for the SOI substrate and exposes the oxide film 302 for SOI, is formed, and further, the oxide film 302 for SOI is selectively removed (FIG. 8A). An undoped polysilicon layer 309 is deposited on the surface of U-shaped trench 306 for contacting with the substrate including a side of an eliminated section 308 of the oxide film 302 for SOI and on the surface of the semiconductor layer 303 for the SOI substrate (FIG. 8B). A spin-on-glass (SOG) layer 310 containing an electroconductive impurity is applied on the undoped polysilicon layer 309. Subsequently, a solid phase diffusion of an impurity is caused from the spin-on-glass layer 310 via a thermal process to provide an electroconductivity to the undoped polysilicon layer 309 (formation of N+ type polysilicon layer 312 provided with an electroconductivity) (FIG. 8C). The spin-on-glass layer 310 on the semiconductor layer 303 for the SOI substrate is selectively removed via an etch back process, and the rest of the spin-on-glass layer 310 remaining on the top surface of the U-shaped trench 306 for contacting with the substrate is planarized (FIG. 9A). In the above process, a power source electrode (not shown) is derived by the N+ type polysilicon layer 312 provided with the electroconductivity through U-shaped trench 306 for contacting with the substrate from the top of the N+ type silicon support substrate 301 to the top of the semiconductor layer 303 for the SOI substrate. It is also described in the document that a contact resistance of such power source electrode on the N+ type silicon support substrate 301 is reduced. Further, a portion of the N+ type polysilicon layer 312 exposed on the upper surface of the substrate is removed (FIG. 9B). An undoped polysilicon is deposited, and an N-type impurity is ion-implanted at a higher concentration on a region serving as a substrate-contacting electrode to form an N+ type substrate contact electrode 311 coupled to the N+ type silicon support substrate 301 through the N+ type polysilicon layer 312.
However, the above-described conventional technologies have to be improved in terms of the following points. In the configuration to shown in FIG. 6, the high-concentration doped polysilicon 109 is employed as an electric conducting path. However, the resistivity is still higher even if polysilicon is doped at higher concentration, and a decrease in the resistance is strictly limited. Therefore, there is still a room of improvement to obtain an electric conducting path with lower resistance.
Besides, Japanese Patent Laid-Open No. S59-232,439 (1984) is directed to a method for forming an element isolation region, and no electric conducting path with lower resistance is obtained. In Japanese Patent Laid-Open No. S59-232,439, a P-type silicon substrate 201, or in other words a low concentration silicon substrate, is employed for a substrate. However, a use of a high concentration substrate is essential for the substrate contact coupled from an upper surface to a back surface of a wafer with lower resistance, a use of a low concentration silicon substrate cannot achieve creating a substrate contact in terms of the characteristics. Further, no contact is formed in the technology disclosed in Japanese Patent Laid-Open No. S 59-232,439.
Further, in Japanese Patent Laid-Open No. H5-109,884 (1993), an electroconductive impurity is diffused to an undoped polysilicon layer from a spin-on-glass layer containing the impurity via a thermal processing. However, a sufficient level of the impurity diffusion from the high concentration spin-on-glass layer is not easy. This is because, in particular, a diffusion coefficient of boron (B) is smaller and the like. Besides, a problem of a difficulty in filling a U-shaped trench with a spin-on-glass without a vacancy is caused. Therefore, an electric conducting path with lower resistance may not be obtained.
The present invention is made based on the above-described circumstances, and the present invention is to provide a semiconductor device having an electric current path from a side of a top surface of a wafer to a substrate with a lower resistance, and also to provide a process for manufacturing thereof.